A method is known for testing electrical characteristics of semiconductor devices, such as VLSI devices, at the wafer level with a conventional thin-type probe card, as disclosed in the lecture archives of the 1988 Annual International Test Conference on Membrane Probe Card Technology, from pages 601 to 607 (hereafter Publication 1). In this conductive test probe as described in Publication 1, wiring was formed by lithography on a flexible dielectric film, and a semi-spherical bump, formed by plating in a through-hole of dielectric film formed at a position matching the electrodes of the semiconductor device-for testing, was utilized as the contact terminal. In the test method described in this Publication 1, the bump, which is connected to the testing circuit by way of the wiring substrate and wiring formed on the surface of the dielectric film, was caused to rub against the electrode of the semiconductor device under test to make contact by a spring effect, and testing was then implemented by an exchange of electrical signals.
Other known methods are described Japanese Laid-Open Patent 2-163664 (hereafter Publication 2), Japanese Laid-Open Patent 5-243344 (hereafter Publication 3), Japanese Laid-Open Patent 8-83824 (hereafter Publication 4), Japanese Laid-Open Patent 8-220138 (hereafter Publication 5), and Japanese Laid-Open Patent 7-283280 (hereafter Publication 6).
In Publication 1 as well as Publications 2, 3, 4 and 5, a testing method is disclosed using a probe device with an automatic offset function having a conveyor means (structure with a lower conductive stage to receive an upper conductive stage installed on a pivot) to make spring contact with a support means to basically form a joint level surface between the flat membrane probe and an essentially flat device under test.
Further, a method is disclosed in the Publications 2, 3, 4 and 5 which proposes to install a cushioning material between the lower conductive stage and the membrane.
Also, in the Publication 5, a method is disclosed for use of a micro-strip line achieved by low-impedance and impedance matching by installing and grounding a metallic conductive layer on the reverse side of a thin conductive pattern formed on a metal protuberance.
Also, in the Publication 6, a method is disclosed for use of a probing device wherein a contact terminal shaped with a point at the tip, obtained by etching a crystalline mold material of anisotropic shape, is connectably embedded in a lead out wiring formed from an insulator film, and this insulator film encloses the silicon wafer forming the substrate and cushioning layer forming a single unit with respect to the wiring substrate.
As described in the above Publication 1, the contact point (protuberance on the electrode) of the probe formed from a flat or semi-spherical bump makes a friction contact, rubbing away the oxidation on the material of the device under test created by a rubbing contact (scribing action) from the aluminum electrode or solder electrode of the probe contact point, and the oxidation is also rubbed away from the electrode material surface to make contact with the conductive metal material at the lower surface. As a result, the scribing action of the electrode at the contact point creates debris from the electrode material causing electrical shorts between the wiring or wiring layers or creating foreign matter. The electrode in many cases is subjected to further damage and wear by the scribing (rubbing) action of the probe which applies a weight of several hundred ni to assure contact with the electrode.
The methods of Publication 2 through Publication 5 have a function for allowing the contact point group to make contact in parallel with the surface of the electrodes of the device under test; however, this structure applies a contact load by displacement of a plate spring so that the spring plate is greatly displaced in terms of a uniform load, making application of a load of several hundred mN per pin necessary when making contact- Consequently, this load creates the problem of damage and wear on the electrodes of the device under test as well as on the active device and wiring directly beneath those electrodes and related problems occurring due to this damage and wear.
In the method of Publication 6, a problem occurs in that absorbing height differences in the contact terminal and electrodes of the device under test, or absorbing the impact received by the contact terminals from driving the material mount holding the device under test during probing, just by means of the cushioning layer is difficult and may also create possible wear and tear on the device under test such as a semiconductor device.
Therefore, none of the known techniques as described above, allows for low load, stable probing of devices under test, such as semiconductor elements having many pins disposed at a narrow pitch caused by high density, without causing damage or wear.